1. Field of the Invention
The present invention relates to an adder for use in a microprocessor which performs operations at high speed, and more particularly to an adder incorporating a Manchester type adder circuit.
2. Description of the Related Art
FIG. 1 is a block diagram showing a 3-bit adder designed for use in a microprocessor which needs to perform operations at high speed. The adder comprises a first shift register 11, a second shift register 12, an ALU (Arithmetic Logic Unit) 13, a third shift register 14, and an AND circuit 15. The first shift register 11 receives 3-bit first input data a. The second shift register 12 receives a 3-bit second input data b. The ALU 13 is a Manchester type adder circuit for receiving the data items f and g output from the shift registers 11 and 12, respectively. The third shift register 14 receives the data h output from the ALU 13. The AND circuit 15 is a two-input circuit for receiving a clock signal CLK and an operation control signal c. The output of the AND circuit 15 is input to the first shift register 11 and also to the second shift register 12. A carry input d is supplied to the ALU 13 from a lower-digit adder, (not shown) and a carry output e is supplied from the ALU 13 to a higher-digit adder (not shown).
FIG. 2 is a timing chart illustrating how the 3-bit adder of FIG. 1 performs static-type addition. In FIG. 2, ta is the decode period during which the adder decodes the operation control signal c, tb is the addition period during which the adder carries out addition, and tc is the setup period during which the third register 14 is set up to store the data h output by the ALU 13.
An addition-instructing code is decoded, rendering the operation control signal c active. At the leading edge of the clock signal CLK, the 3-bit data items f and g are input to the ALU 13 from the shift registers 11 and 12. The ALU performs addition during the period tb, which follows the code-decoding period ta. The result of the addition is stored into the third shift register 14 during the period tc. Hence, the period of ta +tb +tc elapses between the time the adder starts the addition and the time the result of the addition is stored into the third shift register 14.
FIG. 3 is a circuit diagram showing the ALU 13, or a static Manchester-type 3-bit adder 13. The 3-bit adder 13 comprises three adder circuits 70 used for performing addition of a first bit (f0, g0), a second bit (f1, g1) and a third bit (f2, g2) of input data f =(f0, f1, f2) and g =(g0, g1, g2). Each adder circuit 70 has a carrier line 71 and a bus transistor (i.e., a CMOS transfer gate) 72 which connects the carrier line 71 to the carrier line 71 of the immediately following adder circuit. Thus, the adder circuits 70 are connected in series.
Each of the adder circuits 70 further comprises a two-input NAND circuit 73, a two-input NOR circuit 74, a two-input exclusive NOR circuit 75, a two-input exclusive OR circuit 76, an inverter circuit 77, a P-channel transistor 78, and an N-channel transistor 79. The P-channel transistor 78 has its drain-source path connected between a power-supply potential node vcc and the carry line 71, and its gate connected to the output node of the NAND circuit 73. The N-channel transistor 79 has its drain-source path coupled between the carry line 71 and the ground potential node Vss, an its gate connected to the output node of the NOR circuit 74.
It will now be explained how the Manchester-type 3-bit adder (FIG. 3) operates. In the first adder circuit 70, for example, to which the first (f0, g0) of the three bits is input, the NOR circuit 74 outputs "1" when (f0, g0) =(0, 0) is input to the input terminals. The output of the NOR circuit 74 turns on the N-channel transistor 79 since the gate of this transistor 79 is connected to the output node of the NOR circuit 74. As a result, data "0" is output through the carry line 71, regard less of the value of the carry input to this adder circuit from the lower-digit adder circuit. When (f0, g0) =1, 1) is input to the input terminals, the NAND circuit 73 outputs "1". The output of the NAND circuit 73 turns on the p-channel transistor 78 since the gate of this transistor 78 is connected to the output node of the NAND circuit 73. Data "1" is thereby output through the carry line 71, regardless of the value of the carry input to this adder circuit from the lower-digit adder circuit. To the contrary, when (f0, g0) =(1, 0) or (f0, g0) =(0, 1) is input to the input terminals, the NOR circuit 74 outputs "0," whereas the NAND circuit 73 outputs "1." In this case, the N-channel transistor 79 connected to the output of the NOR circuit 74 is turned off, and the P-channel transistor 78 connected to the output of the NAND circuit 73 is turned off. As a result, the output of the exclusive NOR circuit 75 outputs "0." The CMOS transfer gate 72 is thereby turned on, whereby the carry, either "0" or "1", supplied from the lower-digit adder circuit is supplied to the higher-digit adder circuit through the carry line 71. In other words, the carry to the higher-digit adder circuit depends upon the carry supplied from the lower-digit adder circuit.
In the static Manchester-type adder circuit, the carry input from the lower-digit adder circuit is transferred to the upper-digit adder circuit in the case where (0, 1) or (1, 0) is input to the input terminals. Hence, the adder 13 operates at a low speed. If the first, second and third bits (f0, g0), (f1, g1) and (f2, g2) are (0, 1) or (1, 0), the adder 13 operates at the lowest speed. The number of data input to the adder circuits is the square of the number of bits of input data. The more the number of bits of input data, the lower the speed of the adder 13. It is desirable for high speed operation, the carry, whether "0" or "1," be fast transferred from a lower-digit adder circuit to the higher-digit adder circuit.
To increase the operating speed of the Manchester-type adder 13, the adder 13 may be modified into a dynamic one by transferring a carry of only one value, "0" or "1," from a lower-digit adder circuit to the higher-digit adder circuit, and by increasing the speed of the carry transfer. Such a dynamic Manchester-type adder circuit will be described, with reference to FIG. 4.
As is shown in FIG. 4, the dynamic Manchester-type adder circuit is characterized in that a P-channel transistor 80 pre-charges the carry line 71 of each adder circuit 70 to Vcc potential, whereby only a "0" carry is transferred from a lower-digit adder circuit to the higher-digit adder circuit. The P-channel transistor 80 has its source-drain path connected to the Vcc node and the carry line 71 of the third adder circuit 70, and its the gate connected to receive an inverted clock signal CLK.
The dynamic adder shown in FIG. 4 can operate faster than the static adder shown in FIG. 3. However, its use in a system does not increase the operating frequency of the system as a whole. This is because the first half of the clock cycle is spend in pre-charging the the carry lines 71, and only the remaining half of the clock cycle is available for each adder circuit 70 to perform addition.
Due to the P-channel transistor 80, which is used to pre-charge the carry lines 71, the load of each carry line 71 is greater than in the static adder shown in FIG. 3. Obviously, a carry cannot be transferred so fast as desired. Further, in order to pre-charge the carry lines 71, additional hardware must be used, making each adder circuit 70 depend on the carry from the lower-digit adder circuit as in the case where (0, 1) or (1, 0) is input to the input terminals of the adder circuits 70. Due to the use of such additional hardware, the semiconductor chip on which the adder 13 is formed cannot help but have a large pattern area.